SMT Assembly & Advanced Packaging

semiconductor assembly and packagingNew package technologies driving a convergence between the back-end packaging of components and the front end of the assembly process.

Technological innovations in semiconductors and surface mount component packaging continue to increase the complexity and density of electronic components and assemblies, while decreasing the size of components and electronic assemblies. At the same time, there is a never-ending global demand to reduce cost. Miniaturization continues to be a driving force in both integrated circuit packaging and PCB laminate technology.

At present, packaging technology has been the location from the connection, assembly and other general production technology gradually evolved to achieve highly diverse electronic information equipment is one of the key technology. Higher density, smaller bumps, lead-free process needs new package technology, in order to adapt to the consumer electronics market fast changing characteristics of demand. While the development of packaging technology, has also become the semiconductor and electronics manufacturing technology continues to develop powerful pusher, and the former semiconductor technology and surface mount (SMT) technology improvement of significant influence.

If the flip chip bumps generation is a former semiconductor packaging technology backward extension, then, based on the wire bonding chip bump generation is packaging technology forward process extension. It is not difficult for us to observe, the components, systems or the multichip module ( MCM ) package technology, completely changed the package only for the device concept, because MCM technology is set to PCB, SMT hybrid circuit, and semiconductor technology in a collection, so we can call retention device physical prototype system.

In the electronics industry, the new package technology are promoting the manufacturing industry change, appeared on the market integration of active and passive components, analog and digital circuit, even containing the power module encapsulation module, the traditional separation of function mix of technical means, is the rear component package and the front end assembly fusion becomes a trend of. New package technology makes assembly back-end packaging process and mount technology front-end process integration, is likely to trigger a SMT to produce a technology innovation.

Electronic packaging and assembly technologies are growing more complex, and the rate of technological change is accelerating. While surface-mount technology (SMT) is now considered the most mature technology, new developments continue to extend its capabilities to higher levels.

Assembly & Packaging Innovations

In the past decade, interconnect and packaging technologies have become key enablers for advanced microelectronic systems. The world witnessed an amazing growth of smart phones and tablet devices, but also in other domains, microelectronic technologies are becoming pervasive.

In the medical field, electronic devices will be instrumental to control the increasing cost of health care, and in the field of energy, one sees an urgent need for increasing power efficiency. Consequently, we expect a strong increase in the microelectronic content in many applications. .

Recently, industry has consolidated to adopting the 3D-stacked IC approach as the most performing and economically most viable 3D technology for mainstream consumer and high performance applications,

Today, most electronic appliances are rigid, or at most mechanically flexible. In the future, many electronic assemblies on rigid substrates will be replaced by mechanically flexible or even stretchable alternatives. This is a consequence of the ambient intelligence vision where the user carries along more and more electronic systems near the body, on or even inside the body.

These systems must be light weight, take the shape of the object in which they are integrated, and follow all complex movements of these objects, explaining the need for elasticity. Typical examples are implants, intelligent textile, portable electronic equipment (e.g. mobile phones), robotics, car electronics.

The motivation for developing higher density IC packaging continues to be the market and the consumers’ expectation that each new generation of products furnish greater functionality. The miniature IC package evolution began with the development of chip-scale and die-size package technology. These miniature IC package innovations proved ideal for portable and hand-held electronic applications.

To achieve this feat, these products must utilize more advanced packaging methods for the ICs inside the products, as it is the IC packages that hold the footprint to the PCB, thus determining the size of the PCB and, ultimately, the size of the final product. The chip packaging method also determines the speed and performance of that chip, as well as its battery consumption.

These devices are fueling demand for advanced IC packaging technologies such as system-in-package (SiP), stacked packages, fan-in QFNs, fan-out WLPs, interconnection styles of 3D and 2.5D through-silicon vias (TSVs), and flip chip.

Stacked Packages

Stacked packages are essentially a vertical multichip package. They come in many forms, including die stacks, package on package (PoP), package in package (PiP), TSOP stacks, QFNs, MCMs, and WLPs. Now found in all cell phones, stacked packages are enjoying a high-demand market. Stacked package revenue will experience a 10%CAGR through 2015.

Through-Silicon Vias (TSVs)/3-D Interconnect

3D interconnection with TSVs creates a die stack with the shortest interconnection distance, enhancing the characteristics of high speed, low power consumption, reduced parasitics, and small form factor. This interconnection style utilizes vias that go through the silicon to electrically connect one die to the next in a vertical stack in place of wire bonds or other forms of connection.

In a world where small mobile devices connected to the Internet are in high demand, these are important features. By moving to 3D interconnection, the device can achieve 100 times the connectivity or bandwidth with less power consumption. With lines and traces on the silicon die moving to 45-, 32-, and 22-nm lithographies, utilizing TSVs is a way for the back-end interconnection to keep pace with the front-end manufacturing.

The notion of 2.5D was born in early 2010, as a variation of 3D integration. 3D integration stacks devices vertically using TSVs for electrical connection, and possibly an RDL (redistribution layer) created with a dielectric material as a layer to reroute the electrical connections between chips and allow the vias to travel to the lower substrate.

2.5D replaces the RDL with a silicon (or glass) interposer as the routing layer, so that the vias run through the interposer or substrate rather than through the active die. This interposer can be used to fan out or reroute the electrical traces of a device while routing the traces to another vehicle in a vertical dimension, such as the package substrate. These layers utilize microbumps on the interface to electrically connect to the next layer in the stack. Silicon interposers accommodate the CTE mismatch between the layers in a stack, acting as a stress reducer, thus improving reliability.

The identified potential markets for TSVs will climb from 35B units in 2010 to over 54 billion in 2015.

System in Package (SiP)

SiPs are a functional block, a system of electronics that combines functional units together onto a single substrate to enable the shortest electrical distance between parts for superior performance. This reduces the number of traces going into and out of the package, enabling a more simplistic PCB for the final product and potentially reducing system costs. Revenue for SiPs will expand at a 5.4 percent CAGR through 2015.

Fan-In QFNs

To increase the reach of the QFN package involves extending the number of rows of leads from the usual one to two or three rows of leads. The leadframe is stamped or etched as in any other leadframe solution, but the leads are of various lengths, either two or three different lengths. When bent downward for connection to the PCB by trim and form equipment, the result is a multi-row, array-patterned package solution, know as a fan-in QFN. This allows the number of package leads to extend into the hundreds, up from generally fewer than 50. This includes extending its reach to higher bit MCUs and both logic and analog communications chips, largely bound for RF handheld gadgets that require a small-form-factor package. Though the number of fan-in QFNs assembled currently is quite small, the potential is huge, with a projected CAGR of 63.1%through 2015.

Fan-Out WLPs

Reconfigured or fan-out wafer-level packages (WLPs) were introduced in 2006. After devices are manufactured on a wafer, the devices are sawn and transferred on a carrier to another larger wafer that has gaps between die, which are filled with overmold material that also coats the back side of the devices for protection. This allows for a larger surface on which to extend a redistribution layer, thus allowing for far more I/Os than would be possible on the original smaller WLP surface. Solder balls or bumps can be added to this surface for interconnection to a printed circuit board. Fan-Out WLPs have a CAGR of 15.9% for revenue through 2015.

Advanced IC Packages

All these packages are advanced forms of IC packages, which add performance and/or reduced form factor to the mix. These attributes make them suitable for the handheld electronic gadgets that are currently in great demand.

Cellular handsets are the primary handheld electronic gadget that everyone wants to own. Their use is spreading around the world, especially in territories too vast to support wired communication lines. Cellular handsets are growing at an 8.5% CAGR between 2011 and 2015, and the smart phone subset of this market is growing at a 15.2% CAGR. These rates are far greater than for the economy as a whole.

 

Relationship between Semiconductors, SMT, and Microelectronics

Today’s mainstream electronics manufacturing consists mainly of semiconductor packages and surface mount technology processes. Together, the two make up the vast majority of readily acknowledged devices from cell phones to PCs, tablets, and laptops. Even smart high-end toasters leverage these two technologies. The resulting products also end up in automobiles, stereos, TVs, and remote controls. A lesser known technology, however, is working its way into both of these markets – microelectronics.

  1. SMT (Surface Mount Technology) – A motherboard in a PC, or an FR4 board with ICs, resistors, and capacitors reflow soldered making a completed electronic product
  2. Semiconductor – consider lead frame packages with a single IC that is die-attached, wire-bonded, and over-molded. These packages are made by the millions, can be surface mounted, and soldered into through hole substrates/FR4 boards. The number of products built with the technology is staggeringly large.
  3. Hybrid Microelectronics – multiple ICs/packages incorporated into a space-saving package. This can include SMT and semiconductor technologies and can be very complex—mixed technologies that allow for powerful and/or small final products.

Relationship between Semiconductors, SMT, and MicroelectronicsMicroelectronics is a growing packaging method and is working its way into both of these mainstream markets – but in a different way. Both semiconductor and microelectronic packages can utilize the same (or similar) manufacturing techniques. Both can mount bare die with conductive or non-conductive epoxies, or eutectic solders. Both generally employ traditional wire ball bonding for the first level interconnects. These markets are distinct, but they do mix.

Just as SMT technologies incorporate semiconductor packages but rarely the other way around, microelectronics can incorporate both semiconductor and SMT technologies to create complex packages and products.

 

Future Advances

Packaging technology is driven by a combination of cost, performance, form factor and reliability (speed, power and noise immunity), form factor (thickness, weight, PCB area consumption), and testability, as well as the tradeoff of technical maturity versus risk in high-volume manufacturing. With increasing requirements new advances are coming up in conventional back-end packaging, including wafer bumping and copper wire bonding, as well as the role of new 2.5D and 3D integration. New technologies are also making room like, Hybrid Memory Cube, a three-dimensional structure with a logic device at its base and a plurality of DRAMs vertically stacked above it using through-silicon via (TSV) connections.

SMT Equipments – Keeping Pace with New Advances

The need for smaller low-cost packages has triggered SMT equipment manufactures to deliver solutions that can facilitate the production of these tiny semiconductor-based electronic gadgets. The production demands are slowly shifting from low volume to high volume, enabling the SMT equipment manufacturers to contribute systems for faster and better production of these devices.

Listed below are some Advanced SMT Equipments for Assembly & Packaging Industry.

Hitachi High-technologies GmbH

Hitachi High-technologies GmbHHitachi offers great opportunities to help maximize your company values as the world’s leading supplier of SMT & Semiconductor Assembly equipment with our state-of -the-art products.

Technological innovations in semiconductors and surface mount component packaging continues to increase the complexity and density of electronic components and assemblies, while decreasing the size of components and electronic assemblies. At the same time, there is a never-ending global demand to reduce cost. These are the primary parameters that guide this division of Hitachi High Technologies. The Electronic Applied Systems Department (EAD) offers optimal integrated manufacturing solutions to large and small customers by supplying a variety of cutting-edge surface mount technology and semiconductor placement manufacturing solutions.

Universal Instruments’ Advanced Semiconductor Assembly division

Universal Instruments’ Advanced Semiconductor Assembly divisionnd users today have come to expect exceptional capability and power from progressively smaller packages, requiring incredible functional density and dissolving the traditional manufacturing boundaries, all the way from the die to the board. Whether your challenges lie in adopting assembly techniques outside the traditional semiconductor packaging domain, or in extending your SMT offering to wafer and substrate levels, partnering with Universal Instruments’ Advanced Semiconductor Assembly division (ASA) ensures the equipment, expertise and support you need to protect and extend your business.

Universal Instruments’ Advanced Semiconductor Assembly division delivers solutions for the convergence generation. Our high-accuracy technologies extend equipment capabilities into the wafer level domain, allowing you to perform challenging flip chip processes on board or flex, place bare die, and assemble complex optoelectronic components.

We know electronic assembly and packaging technology is a moving target. Our equipment development, knowledge building, and customer support programs are constantly evolving to deliver turnkey solutions today, and the most effective response to the challenges to come.

 

Speedline Technologies class-leading equipment

Speedline Technologies class-leading equipmentSpeedline Technologies serves the electronics assembly and semiconductor packaging industries with class-leading equipment, responsive support and unparalleled process knowledge.

Speedline’s dispensing technology is engineered for the broadest range of component, semiconductor and hybrid assembly packaging applications. The company offers equipment designed to dispense solder paste onto IC substrates, circuit boards and wafers at high throughput rates.

  • Accel – Microelectronics Cleaning Systems
  • Camalot – Dispensing Systems
  • Electrovert – Wave and Reflow Soldering; Inline Cleaners
  • MPM – Stencil and Screen Printers

DEK cost-effective platform for wafer-level processes

DEK cost-effective platform for wafer-level processes creen printing within the semiconductor manufacturing sector falls into two application areas – wafer level packaging and substrate level packaging. Both benefit from the mass imaging capabilities of the precision screen print process delivered on robust DEK printer platforms, and from DEK’s unequalled stencil and screen production process.

Enabling advanced semiconductor packaging and high precision SMT assembly convergence, DEK’s printer platforms are engineered to handle next-generation packages including wafer-level CSPs, flip-chip and ?BGA.